The present invention relates to the generation of random patterns in electronic circuits. In particular, it relates to a method and system for controlling the weight of a random bit pattern generated in an electronic circuit.
A technical area in which the present invention can be preferably applied is in integrated circuits, which are provided with logic circuits and self-test circuits for testing the logic circuits. Such built-in self-test technology is used in a wide spread plurality of technical devices, which have a more or less chip-controlled operation mode. Examples are chips in a motherboard of a computer, printers, and other electronic devices. The need for self-test technology is present due to the fact that complex very large-scale integrated circuit devices are fabricated on a single semiconductor chip and contain millions of functional circuit elements. For testing all these circuit elements, a very huge number of deterministic test patterns are necessary. Most of the circuit elements could be tested with Build-In-Self-Test (BIST) using weighted random test pattern. A small rest of complex patterns is then tested with deterministic test pattern.
If, by way of example, a semiconductor chip is provided with fifty input connections, the number of combinations of inputs is 250. While one could apply that number of different input patterns, record the output responses, and compare those responses with the responses that ought to result, this would be an unacceptable work as it would last much too long and is thus impossible for a modern production testing.
U.S. Pat. No. 5,983,380 to IBM corporation discloses a built-in self-test design (BIST), a weighted random pattern (WRP), and deterministic pattern test methodologies which correspond to the current state of the art in support of level-sensitive scan device (LSSD) logic and structural testing, which is today the prevailing main design and test approach. This prior art approach utilizes a linear feedback shift register (LFSR) 12, see FIG. 1 and FIG. 6, which applies test vectors to an integrated circuit device under test which is in turn not explicitly depicted. The test vector includes bit locations of a predetermined length, which are filled with a weighted random bit pattern.
A control logic 14 comprising a plurality of AND-gates 15 the outputs of which are connected to the input of a common OR-gate 16 is fed with random bits coming from a predetermined plurality of tap locations from the LFSR 12, and with a predetermined plurality of control inputs the number of which defines the number of different possible weights for the generated random bit pattern.
A disadvantage of this prior art approach is that a lot of chip area is required for implementing the control circuit 14 and the additional wiring of the control lines. Further, the separate (not depicted) control circuit required for generating the control inputs for said circuit 14. Said control inputs are denoted with reference sign 17.
This disadvantage is the more intolerable the wider are decoders or multiplexers which must be tested with a wide sequence of “0” or “1” bit in parallel, as in such cases the control overhead is consuming an intolerable fraction of chip area.